Calibre
The gold standard for silicon signoff
Calibre is the de facto industry standard for IC physical verification and design for manufacturability, covering DRC, LVS, parasitic extraction and litho-friendly design.
A tape-out is expensive enough that physical verification before manufacturing release is the last and most critical gate. Calibre holds certified status at virtually every major foundry — their standard verification rule decks are delivered in Calibre format.
Its value is not merely reporting errors but handling verification volume that explodes at advanced nodes: full-chip runs on hundreds of millions to billions of devices demand extreme parallel efficiency and incremental verification. That engineering depth is hard to displace.
Key capabilities
DRC
Full-chip design rule checking, supporting complex advanced-node rule sets.
LVS
Layout versus schematic consistency verification.
Parasitic extraction
High-accuracy extraction for post-layout simulation and timing signoff.
DFM
Litho-friendly design and yield improvement analysis.
Massive parallelism
Large-scale distributed computing for very large designs.
Foundry certified
Certified by major foundries, so signoff results are accepted directly.
What it delivers
- Certified by major foundries, so signoff output is usable as delivered
- Handles very large designs with manageable turnaround
- Incremental verification avoids full-chip reruns every time
- DFM capability lifts yield directly
- Mature debug and error location tools shorten fix cycles
Modules & components
Typical applications
More products
Tessent
Make silicon testable, diagnosable and self-aware
View all productsQuesta
Functional coverage decides whether you dare tape out
View all productsXpedition
Enterprise-grade PCB design at high density
View all products