Tessent
Make silicon testable, diagnosable and self-aware
Tessent is a silicon lifecycle management solution covering design for test, test pattern generation, yield analysis and on-chip monitoring — spanning design through volume production.
How efficiently a chip can be tested for defects depends largely on whether testing was planned during design. Tessent inserts scan chains, compression structures and built-in self-test logic so pattern generation is automated and test time and cost are contained.
The other half of its value arrives after production ramp: on-chip monitoring structures and yield analysis feed failure information back into design and manufacturing, closing the loop. At high volume, a single yield point can be a material profit difference.
Key capabilities
Scan and compression DFT
Automatic insertion of scan chains and test compression to lower test cost.
ATPG
Automatic generation of high-coverage test patterns.
Built-in self-test
On-chip self-test structures for memory and logic.
Yield analysis
Failure analysis and yield root-cause localisation.
On-chip monitoring
Embedded structures reporting field operating conditions.
Boundary scan
Support for IEEE 1149.1 and IEEE 1687 interfaces.
What it delivers
- Coverage targets met while test time stays under control
- Highly automated DFT with minimal intrusion on the design flow
- Production yield analysable down to root cause
- On-chip monitoring supports long-term reliability management
- Spans design to volume production, spreading return over a long life
Modules & components
Typical applications
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